IC62LV1008L Datasheet, PDF (2/11 Pages) Integrated Circuit Solution Inc – 1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM

IC62LV1008L
IC62LV1008LL
1M x 8 LOW POWER and LOW VCC
CMOS STATIC RAM
Preliminary
FEATURES
• Access times of 55, 70, 100 ns
• CMOS Low power operation:
ICC=15mA (typical)* operation
ISB2=2µA (typical)* standby
• Low data retention voltage: 1.5V (min.)
• Output Enable (OE) and Two Chip Enables
(CE1, CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
— No clock or refresh reguired
• Single 2.7V-3.6V power supply
• Wafer level burn in test mode
• Available in the know good die form and
48-pin 8*10mm TF-BGA
* Typical values are measured at VCC=3.0V, TA=25°C
DESCRIPTION
The ICSI IC62LV1008L and IC62LV1008LL is a low voltage,
1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using
ICSI's low voltage, six transistor (6T), CMOS technology. The
device is targeted to satisfy the demands of the state-of-the-art
technologies such as cell phones and pagers.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels. Additionally, easy
memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable ( WE)
controls both writing and reading of the memory.
The IC62LV1008L and IC62LV1008LL are available in know
good die form and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A19
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
1024K x 8
MEMORY ARRAY
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001