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IC61S6432 Datasheet, PDF (18/21 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM | |||
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IC61S6432
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating
Range) (Continued)
Symbol
Parameter
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
10 â 12 â 13 â 15 â
ns
tKH
Clock High Time
3.5 â 4 â 6 â 6 â
ns
tKL
Clock Low Time
3.5 â 4 â 6 â 6 â
ns
tKQ
Clock Access Time
â5 â6 â7â8
ns
tKQX(2)
Clock High to Output Invalid
1.5 â 1.5 â 2 â 2 â
ns
tKQLZ(2,3)
Clock High to Output Low-Z
0â 0â 0â0â
ns
tKQHZ(2,3)
Clock High to Output High-Z
1.5 6 1.5 6
2626
ns
tOEQ
Output Enable to Output Valid
â5 â6 â6â6
ns
tOEQX(2)
Output Disable to Output Invalid
0â 0â 0â0â
ns
tOELZ(2,3)
Output Enable to Output Low-Z
0â 0â 0â0â
ns
tOEHZ(2,3)
Output Disable to Output High-Z
â4 â5 â6â6
ns
tAS
Address Setup Time
2.5 â 2.5 â 2.5 â 2.5 â
ns
tSS
Address Status Setup Time
2.5 â 2.5 â 2.5 â 2.5 â
ns
tCES
Chip Enable Setup Time
2.5 â 2.5 â 2.5 â 2.5 â
ns
tAH
Address Hold Time
2.5 â 2.5 â 2.5 â 2.5 â
ns
tSH
Address Status Hold Time
2.5 â 2.5 â 2.5 â 2.5 â
ns
tCEH
Chip Enable Hold Time
2.5 â 2.5 â 2.5 â 2.5 â
ns
tZZS(4)
ZZ Standby
2â
2â
2â2â
cyc
tZZREC(5)
ZZ Recovery
2â
2â
2â2â
cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
5. ADSC and ADSP must not be asserted for at least two cycles after leaving ZZ state.
18
Integrated Circuit Solution Inc.
SSR016-0A 09/13/2001
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