IC61S6432 Datasheet, PDF (13/21 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

IC61S6432
WRITE CYCLE TIMING
CLK
ADSP
ADSC
ADV
A15-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
tKC
tKH
tKL
tSS
tSH
ADV must be inactive for ADSP Write ^tAVS
tAS
tAH
WR1
tWS
WR2
tWH
ADSP is blocked by CE1 inactive
ADSC initiate Write
tAVH
WR3
tWS
tWH
tWS
tWH
tWS
tWH
WR1
WR2
WR3
tCES
tCEH
CE1 Masks ADSP
tCES
tCEH
CE2 and CE3 only sampled with ADSP or ADSC
tCES
tCEH
Unselected with CE2
OE
DATAOUT
High-Z
tDS
tDH _{BW4-BW1 only are applied to first cycle of WR2}
DATAIN
High-Z
1a
2a
2b
2c
2d
3a
Single Write
Burst Write
Write
Unselected
Integrated Circuit Solution Inc.
13
SSR016-0A 09/13/2001