IC61S6432 Datasheet, PDF (16/21 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

IC61S6432
READ/WRITE CYCLE TIMING: PIPELINE
CLK
ADSP
ADSC
tKC
tKH
tKL
tSS
tSH
tSS
tSH
ADSP is blocked by CE1 inactive
ADV
A15-A0
GW
BWE
BW4-BW1
CE1
CE2
CE3
OE
DATAOUT
DATAIN
tAS
tAH
RD1
WR1
RD2
tWS
tWH
tWS
tWH
tCES
tCEH
tWS
tWH
WR1
CE1 Masks ADSP
tCES
tCEH
tCES
tCEH
tOEQ
CE2 and CE3 only sampled with ADSP or ADSC
tOEHZ
High-Z
High-Z
tOELZ
tKQLZ
tKQ
Single Read
tOEQX
1a
tKQX
tKQHZ
1a
tDS
tDH
Single Write
2a
2b
2c
Burst Read
RD3
Unselected with CE3
tKQX
2d
tKQHZ
Unselected
16
Integrated Circuit Solution Inc.
SSR016-0A 09/13/2001