IC61S6432 Datasheet, PDF (14/21 Pages) Integrated Circuit Solution Inc – 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

IC61S6432
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
-200⁽¹⁾
-166
-133
-117
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
5 — 6 — 7.5 — 8.5 —
ns
tKH
Clock High Time
1.6 — 2.4 — 2.8 — 3 —
ns
tKL
Clock Low Time
1.6 — 2.4 — 2.8 — 3 —
ns
tKQ
Clock Access Time
—4 —5 —5—5
ns
tKQX⁽²⁾
Clock High to Output Invalid
1 — 1.5 — 1.5 — 1.5 —
ns
tKQLZ^(2,3)
Clock High to Output Low-Z
— 0— 0—0—
ns
tKQHZ^(2,3)
Clock High to Output High-Z
1 3.5 1.5 5 1.5 5 1.5 6
ns
tOEQ
Output Enable to Output Valid
— 3.5 — 5 — 5 — 5
ns
tOEQX⁽²⁾
Output Disable to Output Invalid
0— 0— 0—0—
ns
tOELZ^(2,3)
Output Enable to Output Low-Z
0— 0— 0—0—
ns
tOEHZ^(2,3)
Output Disable to Output High-Z
—3 —3 —3—4
ns
tAS
Address Setup Time
2 — 2.5 — 2.5 — 2.5 —
ns
tSS
Address Status Setup Time
2 — 2.5 — 2.5 — 2.5 —
ns
tWS
Write Setup Time
2 — 2.5 — 2.5 — 2.5 —
ns
tCES
Chip Enable Setup Time
2 — 2.5 — 2.5 — 2.5 —
ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tWH
Write Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCEH
Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 —
ns
tCFG⁽⁴⁾
Configuration Setup
25 — 25 — 30 — 35 —
ns
Notes:
1. ADVANCE INFORMATION ONLY.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. Configuration signal MODE is static and must not change during normal operation.
14
Integrated Circuit Solution Inc.
SSR016-0A 09/13/2001