IC-MQF_15 Datasheet, PDF (28/38 Pages) IC-Haus GmbH – Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MQF PROGRAMMABLE 12-BIT ^preliminary
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
OUTPUT SETTINGS AND ZERO SIGNAL
Rev C1, Page 28/38
The interpolation factor IPF determines the number of
A/B signal cycles per input signal period. These A/B
signal cycles are counted in the internal register POS,
which can be used to blank the zero pulse.
POS is set to 0 if the input sine/cosine phase angle is
zero degrees, its maximum value is POS_max = IPF-1.
The internal A/B signal cycle adheres to the following
pattern:
A1100
B1001
Zero Signal Generation
The generation of the zero signal is dependant on the
internal signal Z_In which is produced by comparing the
calibrated CH0 input signals. The offset calibration of
CH0 influences the width of the Z_In signal. The correct
position of Z_In should be checked before configuring
the zero signal blanking logic. This is possible by com-
paring the Z_In signal with the PA/PB signals in Mode
ABZ: Z_In is displayed on pin ERR if EMASKA = 0x010
and EMTD = 0x0 is programmed.
Table 40: Internal A/B Signal Cycle
Inversions and reversals can be selected for the output
of the A/B/Z signals and the zero signal can be blanked
with any combination of the internal A and B signal by
programming parameter CFGABZ.
CFGABZ
Bit
7
6
5
4
3
2
1
0
Addr 0x1D, bit 7:0
Function and Description
Output inversion for channel A: PA<>NA
PA = P1i xor CFGABZ(7)
Output inversion for channel B: PB<>NB
PB = P2i xor CFGABZ(6)
Output inversion for index channel: PZ<>NZ
PZ = P0i xor CFGABZ(5)
Exchange of the A/B signals
0: P1i = A, P2i = B
1: P1i = B, P2i = A
Zero Signal Blanking CFGABZ(3:0)
Enable for A = 1, B = 1
Enable for A = 1, B = 0
Enable for A = 0, B = 0
Enable for A = 0, B = 1
Table 41: Output Logic
Figure 10: Signal path from Z_In to PZ/NZ
The blanking of the Z_In signal by CFGZPOS is relative
to the internal A/B cycle count POS. Multiple settings
of CFGZPOS are possible at high resolutions, choose
a setting which centers the output signal PZ in relation
to Z_In. Attention: Programming CFGZPOS to a cycle
count larger than POS_max leads to undetermined zero
signal prevention.
CFGZPOS
Bit
7
(6:0)
Example
Addr 0x1E, bit 7:0
Description
0: Mask not used
1: Mask Enable
(zero signal blanking with POS enabled)
For IPF < 200:
blanking of Z_In if POS ̸= CFGZPOS(6:0)
For IPF≥ 200:
blanking of Z_In if POS ̸= 8 * CFGZPOS(6:0)
Assuming an index window where sine crosses
cosine (45 °):
CFGZPOS = 13 for IPF 100, respectively
CFGZPOS = 16 for IPF 1000
Table 42: Zero Signal Positioning
Figure 9: Signal Path from A and B to PA/NA and
PB/NB
ENZFF
Code
0
1
Note
Addr 0x02, bit 4
Description
Zero signal output with state change of P0i
Zero signal output synchronized with A/B signal
This function requires an index gating window Z_in
that fully overlaps the selected AB cycle for indexing.
Table 43: Zero Signal Synchronization