IC-MH Datasheet, PDF (21/23 Pages) IC-Haus GmbH – 12 BIT ANGULAR HALL ENCODER

iC-MH
12 BIT ANGULAR HALL ENCODER
OTP Programming
Rev B1, Page 21/23
CFGPROT
0
1
Adr 0x05; Bit 6
no protection
write/read protection
Table 32: Write/read protection of configuration
With CFGPROT = ’0’, the registers at the addresses
0x00 to 0x0F and 0x78 to 0x7F are readable and write-
able. The addresses 0x10 to 0x1F and 0x77 are read-
only. With CFGPROT = ’1’, all registers except the ad-
dresses 0x7B and 0x7C are write-protected; the ad-
dresses 0x77 to 0x7F are readable, while all others
are read-protected.
100nF
100nF
VPA
VPD
VZAP
iC-MH MA
SLI
SLO
VNA
VND
100nF
+ 10uF
+5V
+7V Programming
Board
Serial
Interface
0V
START
SET CONFIGURATION
SET CIBM = 0x0
START HW ZAP ALGORITHM
SET ADR 0x0F = 0x01
VPD = VPA = 5.0V
FALSE
FALSE
VERIFY
VPD = VPA = 5.5V
CIBM = 0x0
TRUE
VERIFY
VPD = VPA = 4.0V
CIBM = 0xF
TRUE
CIBM programmed?
TRUE
STOP
SET CIBM
FALSE
Figure 25: Programming within system
Figure 26: Programming algorithm
An internal programming algorithm for the ZAP diodes
is started by setting the bit PROGZAP. This process
can only be successful, if the voltage difference be-
tween VZAP and VNA pin is within the specified value
and the test register is set to TEST = 0x00. Following
programming, the PROGZAP bit is reset automatically.
In the process, the bit PROGOK is set in the status reg-
ister (address 0x77) when programming is successful,
and the bit PROGERR, if it is not.
A 100 nF ceramic block capacitor must be placed on
board directly between VZAP and VNA pins of the iC-
MH. Also a 10 µF capacitor must be present at the
end of the programming line as close to the connec-
tor as possible (see figure 25). During programming
up to 100 mA flow from pin VZAP to pin VNA, making
it necessary to ensure proper PCB layout to minimize
voltage drops.
Once the device has been successfully calibrated the
configuration can be written into the device. To this
end the contents of the RAM bits are transferred to
the ROM zapping structure. CIBM is first set to 0x0
at address 0x04 and the hardware programming algo-
rithm started by bit PROGZAP. Programming should
be monitored with the threshold settings for CIBM and
VPD, VPA voltage by reading out the ZAP structures
via the serial interface. If programming is not success-
ful, the hardware programming algorithm can again be
initiated. In the second stage of the procedure the bias
current is programmed in the CIBM register. Here, all
RAM bits are set to 0x00; register CIBM is configured
with the calculated calibration value and the program-
ming algorithm started. Programming is successful
when all bits have been configured.