IC-MG_14 Datasheet, PDF (2/22 Pages) IC-Haus GmbH – 8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MG
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D1, Page 2/22
DESCRIPTION
iC-MG is a non-linear A/D converter which, by apply-
ing a count-safe vector principle, digitizes sine/cosine
sensor signals with selectable resolution and hys-
teresis. The angle position is output incrementally via
differential RS422 drivers as an encoder quadrature
signal with an index pulse. The minimum phase dis-
tance can be preselected, to enhance the systems’s
noise immunity and to allow for fail-safe counting.
The PGA front-end permits differential (VDIFF or ID-
IFF mode) or single-ended input signals (VREF or
IREF mode); high impedance (V modes) and low
impedance (I modes) can be selected. By this adap-
tation MR sensor bridges or photosensors can be di-
rectly connected.
The integrated signal conditioning unit allows signal
amplitudes and offset voltages to be calibrated and
also any phase error between the sine and cosine
signals to be corrected.
For the purpose of signal stabilization (to minimize
the effects of temperature and aging), the chip’s
power supply controller can take over LED control in
optical systems (40 mA current-source output PWR).
If MR sensors are connected this driver stage also
powers the measuring bridges. If the control thresh-
olds are reached this is signaled at alarm message
output NERR (signal loss due to wire breakage, short
circuiting, dirt or aging, for example).
iC-MG is protected against a reversed power supply
voltage; the integrated supply switch for loads of up
to 20 mA extends this protection to cover the over-
all system. The device is configured via an external
EEPROM.
PACKAGING INFORMATION
PIN CONFIGURATION TSSOP20
PIN FUNCTIONS
No. Name Function
1 PZERO Input Zero Signal +
2 NZERO Input Zero Signal -
3 NSIN Input Sine Signal -
4 PSIN Input Sine Signal +
5 VDDS¹⁾ Switched Supply Output and Internal
Analog Supply Voltage
(reverse pol. proof, load 20 mA max.)
6 GNDS¹⁾ Switched Ground (reverse pol. proof)
7 PCOS Input Cosine Signal +
8 NCOS Input Cosine Signal -
9 PWR Controlled Power Supply Output
(high-side current source)
10 SDA Serial E2PROM Interface, data line
11 SCL Serial E2PROM Interface, clock line
12 NB
Incremental Output B-
13 B
Incremental Output B+
14 NA
Incremental Output A-
15 A
Incremental Output A+
16 GND Ground
17 VDD +4.3 ... 5.5 V Supply Voltage
18 NZ
Incremental Index Output Z-
19 Z
Incremental Index Output Z+
20 NERR Alarm Message and Test Signal Out-
put (e.g. index enable signal Zin)
1) It is advicable to connect a bypass capacitor of at least 100 nF close to the chip’s analog supply terminals.