IC-MG_14 Datasheet, PDF(11/22 Page) IC-Haus GmbH – 8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

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IC-MG_14 Datasheet, PDF (11/22 Pages) IC-Haus GmbH – 8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

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iC-MG

8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

OPERATING MODES

Rev D1, Page 11/22

MODE

Code

0x00

0x01

0x02

0x0B

Adr 0x02, bit 3:0

Operating Mode

Pin A

Pin NA

Pin B

ABZ Mode

Calibration Mode 1

VREFIZ

VREFISC

Calibration Mode 2

PCH-S

NCH-S

PCH-C

System Test Mode *

* Note: Setting SELRES = 0x1B0 and SELHYS = 0xF is mandatory.

Pin NB

IBN

NCH-C

Pin Z

PCH-Z

VDCS

ZIn

Pin NZ

NCH-Z

VDCC

NERR

Table 5: Operating Modes

iC-MG has several modes of operation which are set

via MODE. In addition to the primary operational mode

ABZ Mode for the output of encoder quadrature sig-

nals via differential line drivers both analog and digital

calibration signals can be selected which can be used

to set up the integrated signal conditioning unit.

ABZ Mode

In ABZ Mode complementary signals are always out-

put. Here, converter setting SELRES determines the

A/B pulse count and zero signal settings CFGZ and

CFGPOS the width and position of the generated zero

signal (dependent on an enable from ZIn).

In Calibration Mode 2 the conditioned sine and cosine

signals are output (signals PCH-S, NCH-S, PCH-C

and NCH-C). Additionally, the intermediate potentials

of both input channels are also available, with VDCS

for the sine and VDCC for the cosine channel. The

calibration of these intermediate voltages is described

on page 14.

System Test Mode

System Test Mode permits the ï¬ne adjustment of the

sine and cosine input signals using digital signals. The

registers mentioned above must also be set for this

mode.

Calibration Mode 1, Mode 2

So that signal amplitudes and offset voltages can be

calibrated internal analog signals are switched to the

output pins directly and the digital line drivers shut

down. Due to internal resistances of up to 4 kâ¦ a high-

impedance measurement is advisable.

In Calibration Mode 1 bias current source IBN and the

internal zero signal are available after the input am-

pliï¬er (signals PCH-Z and NCH-Z). The calibration of

IBN is described on page 11, that of the zero signal on

page 15.

The A4 duty cycle acts as a measure for the offset of

the sine channel, with the B4 duty cycle a measure for

that of the cosine channel. The duty cycle at A8 repre-

sents the phase error between sine and cosine or any

deviation from the ideal value of 90â¦. The calibration

of differing signal amplitudes enables the duty cycle at

B8. A duty cycle of 50 % is the calibration target for all

digital test signals.

Signal ZIn is the unmasked digitized zero signal.

BIAS CURRENT SOURCE CALIBRATION

The calibration of the bias current source in operation

mode Calibration 1 is prerequisite for adherence to the

given electrical characteristics and also instrumental

in the determination of the chip timing (e.g. clock fre-

quency at SCL). For setup purposes the IBN bias cur-

rent is measured using a 10 kâ¦ resistor by pin VDDS

connected to pin NB. The setpoint is 200 ÂµA which is

equivalent to a voltage drop of 2 V.

NOTE: The measurement delivers a false reading

when outputs are tristate (due to a conï¬guration error

after cycling power, for instance).

CFGIBN

Code k

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Adr 0x01, bit 7:4

IBN

â¼

39âk

79 %

81 %

84 %

86 %

88 %

91 %

94 %

97 %

Code k

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

IBN

â¼

39âk

100 %

103 %

107 %

111 %

115 %

119 %

124 %

129 %

Table 6: Bias Current Source Calibration

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