IC-MG_14 Datasheet, PDF(18/22 Page) IC-Haus GmbH – 8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

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IC-MG_14 Datasheet, PDF (18/22 Pages) IC-Haus GmbH – 8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

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iC-MG

8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

OUTPUT SETTINGS

Rev D1, Page 18/22

Conï¬guration of Output Drivers

The output drivers can be used as push-pull, lowside

or highside drivers. TRIHL(1:0) selects the mode of

operation. In order to avoid steep edges during trans-

mission via short cables the slew rate can be reduced

using SSR (tolerances as given in Electrical Charac-

teristics).

TRIHL

Code

Adr 0x1E, bit 1:0

Function

Push-pull operation

Highside driver mode (P channel open drain)

Lowside driver mode (N channel open drain)

Not permitted

Table 31: Output Drive Mode

SSR

Code

Note

Adr 0x1E, bit 3:2

Function

Nominal value 25 ns

Nominal value 80 ns

Entries 00 and 11 are not permitted

Zero Signal Positioning

The output of the zero pulse, generated internally, is

based on an enable from ZIn which can be observed in

System Test Mode and in ABZ Mode at pin NERR (via

EMASKA= 0x010 and EMTD= 0x0). As the offset cali-

bration of the zero signal alters the signal width the cor-

rect position and width of signal ZIn should be checked

before the digital conï¬guration parameters are deter-

mined.

The zero pulse output position can be selected via

CFGZPOS(6:0); the cycle count begins with the sine

zero crossing. No zero pulse is output for all values

which are either greater than or equal to the interpola-

tion factor.

CFGZPOS

Bit

6:0

Adr 0x1A, bit 7:0

Function

Enables the selection below

Count of A/B period releasing the Z output

Table 34: Zero Signal Positioning

Table 32: Output Slew Rate

Minimum Phase Distance

The minimum phase distance for the A/B and Z output

signals can be preselected using MTD(3:0). This set-

ting limits the maximum possible output frequency for

secure transmission to counters which are either un-

able to debounce noise spikes or only permit low input

frequencies.

CFGZ

Code

1ddd

d1dd

dd1d

ddd1

Notes

Adr 0x19, bit 3:0

Function

Enables Z= 1 with A= 1, B= 1

Enables Z= 1 with A= 1, B= 0

Enables Z= 1 with A= 0, B= 0

Enables Z= 1 with A= 0, B= 1

d = donât care; any combination is permissible.

Table 35: Zero Signal Logic

MTD

Code

0x8

0x9

...

0xE

0xF

Note

Adr 0x1D, bit 7:4

Function

200 ns

400 ns

...

1.4 Âµs

1.6 Âµs

Codes 0x0 to 0x7 are not permitted.

All timing speciï¬cations are nominal values, see

Elec. Char. No. 511 for tolerances.

Table 33: Minimum Phase Distance

When selecting the minimum phase distance the slew

rate setting of the RS422 output drivers and the length

of cable used must be taken into consideration.

Figure 4: Zero Signal Gating Examples

(example for CFGZPOS(7)=1, CFGZ-

POS(6:0)=0x6)

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