IC-MG_14 Datasheet, PDF (12/22 Pages) IC-Haus GmbH – 8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

iC-MG
8-Bit Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
INPUT CONFIGURATIONS
Rev D1, Page 12/22
All input stages are configured as instrumentation am-
plifiers and thus directly suitable for differential input
signals. Referenced input signals can be processed
as required; in Single-Ended Input Mode the NZERO
input acts as a reference, replacing the input signals
from NSIN and NCOS. Both current and voltage sig-
nals can be processed as input signals, selected by
RSC(0) and RZ(0).
ca. 25%. The circuitry is equivalent to the resistor
chain in I Mode; the pad wiring resistor is considerably
larger here, however.
INMODE
Code
0
1
Note
Adr 0x03, bit 2
Function
Differential input signals
Single-ended input signals *
* Input NZERO is reference for all inputs.
Table 7: Input Signal Mode
Figure 1: Input instrumentation amplifier and signal
conditioning
Current Signals
In I Mode an input resistor Rin() becomes active at
each input pin, converting the current signal into a volt-
age signal. The input resistance Rin() consists of a pad
wiring resistor and resistor Rui() which is linked to the
adjustable bias voltage source VREFin().
The following table shows the possible selections, with
Rin() giving the typical resulting input resistance (see
Electrical Characteristics for tolerances). The input re-
sistor should be set in such a way that intermediate
potentials VDCS and VDCC lie between 125 mV and
250 mV (verifiable in Calibration Mode 2).
NB. The input circuit is not suitable for back-to-back
photodiodes.
Voltage Signals
In V Mode an optional voltage divider can be selected
which reduces unacceptably large input amplitudes to
RSC
RZ
Code
–000
–010
–100
–110
1—1
0—1
Notes
Adr 0x0E, bit 3:0
Adr 0x13, bit 3:0
Nominal Rin() Internal Rui() I/V Mode
1.7 kΩ
1.6 kΩ
Current input
2.5 kΩ
2.3 kΩ
Current input
3.5 kΩ
3.2 kΩ
Current input
4.9 kΩ
4.6 kΩ
Current input
20 kΩ
5 kΩ
Voltage input 4:1*
high
impedance
1 MΩ
Voltage input 1:1
For single-ended signals identical settings of RIN0
and RIN12 are required.
*) VREFin is the voltage divider’s footpoint. Input
currents may be positive or negative (Vin > VREFin,
or Vin < VREFin)
Table 8: I/V Mode and Input Resistance
BIASSC
BIASZ
Code
0
1
Adr 0x0E, bit 6
Adr 0x13, bit 6
Function
VREFin = 2.5 V
for low-side current sinks (e.g. photodiodes with
common anode at GNDS)
VREFin = 1.5 V
for high-side currrent-sources (e.g. photodiodes
with common cathode at VDDS)
for voltage sources versus ground
(e.g. iC-SM2, Wheatstone sensor bridges)
Table 9: Input Bias Voltage