IC-TW3 Datasheet, PDF (15/24 Pages) IC-Haus GmbH – SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER

iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
Rev B1, Page 15/24
set of the input signal. Note that COFSA(5:0) and
COFSB(5:0) are in 2’s complement format and their
value range is limited from -31 to +31.
CGAINA(2:0)
Adr 0x07; Bit 2:0
R/W
CGAINB(2:0)
Adr 0x07; Bit 5:3
R/W
Code
gain = cgain x 6 dB
0x00
0 dB (default)
0x01
6 dB
...
0x06
36 dB
Table 11: Coarse gain select for channel A/B
COFSA(7:0)
Adr 0x08; Bit 7:0
COFSB(7:0)
Adr 0x09; Bit 7:0
Code 2’K Code 5:0, and decimal
0xE1
0x21, -31
...
...
0xFF
0x3F, -1
0x00
0x00, 0
0x01
0x01, +1
...
...
0x1F
0x1F, +31
R/W
R/W
offset = cofs x 40 mV
-1240 mV
-40 mV
0 mV (default)
40 mV
1240 mV
Table 12: Coarse offset select for channel A/B
enabled the values of FGAINA/B and FOFSA/B are
equal to the register values in DGAINA/B(7:0) and
DOFSA/B(7:0). Refer to chapter "Temperature Com-
pensation" on page 21 for a detailed explanation of fine
gain and fine offset calculations. DGAINA/B(7:0) and
DOFSA/B(7:0) can be programmed to a fixed value or
it is automatically updated when dynamic adaption is
enabled.
Output driver
The output amplifier is capable of driving a 100 Ω dif-
ferential load and is stable with capacitive loads of up
to 100 nF. Control register OGAIN(1:0) is used to se-
lect the output amplifier gain. A gain of -3 dB is useful
to accommodate input signals larger than 1 V and gain
of +6 dB will provide a 1 Vpp single-ended output. Note
that the selected output amplifier gain will influence the
automatic gain compensation. Refer to section "Auto-
matic Compensation" on page 18 for details.
OGAIN(1:0)
Adr 0x01; Bit 7:6
R/W
Code
Function
0x00
0 dB (default)
0x01
reserved
0x02
+6 dB
0x03
-3 dB
DGAINA(7:0)
Adr 0x0A; Bit 7:0
R/W
DGAINB(7:0)
Adr 0x0B; Bit 7:0
R/W
Code
gain = dgain x 0.08 dB - 2 dB
0x00
-2 dB (default)
...
0x19
0 dB
0x1A
0.08 dB
...
0xFF
18.4 dB
Table 13: Dynamic gain select for channel A/B
DOFSA(7:0)
Adr 0x0C; Bit 7:0
R/W
DOFSB(7:0)
Adr 0x0D; Bit 7:0
R/W
Code
offset = cofs x 2 mV
0x81
-254 mV
...
0xFF
-2 mV
0x00
0 mV (default)
0x01
2 mV
...
0x7F
254 mV
Table 14: Dynamic offset select for channel A/B
Value FGAINA/B and FOFSA/B are fine gain and off-
set control respectively. They are calculated dynam-
ically according to the temperature compensation al-
gorithm. In case temperature compensation is not
Table 15: Output amplifier gain on channel A/B
A programmable 1^st-order low-pass filter can be en-
abled to limit the path bandwidth. The filter cut-off fre-
quency can be set via the FILTER(1:0) register.
FILTER(1:0)
Adr 0x04; Bit 4:3
R/W
Code
Function
0x00
1 MHz (default)
0x01
500 kHz
0x02
200 kHz
0x03
reserved
Table 16: Signal path filter
In order to save power the complete signal path can be
disabled using the control bits PDA and PDB respec-
tively. When disabled the outputs are high impedance.
The dynamic adaption should be disabled when either
channel A or B is disabled.
PDA
Adr 0x04; Bit 0
R/W
PDB
Adr 0x04; Bit 1
R/W
Code
Function
0
Channel A/B is enabled (default)
1
Channel A/B is powered down
Table 17: Power down control on channel A/B