IC-TW3 Datasheet, PDF (11/24 Pages) IC-Haus GmbH – SENSOR SIGNAL CONDITIONER WITH TEMPERATURE COMPENSATION AND LINE DRIVER

iC-TW3 SENSOR SIGNAL CONDITIONER WITH
TEMPERATURE COMPENSATION AND LINE DRIVER
I2C INTERFACE
Rev B1, Page 11/24
Startup
An external I²C 1-kbit EEPROM (e.g. 24xx01 family)
is used to store configuration parameters permanently.
On power-up and after reset is released iC-TW3 ac-
cesses the external EEPROM and reads its device
configuration according to Table 6.
EEPROM Checksum
The checksum at address 0x0F contains the 8-bit sum
of registers 0x01 to 0x0E plus the 8-bit sum of all LUT
bytes up to and including the final block with its break-
point set to 255.
On startup iC-TW3 calculates the expected checksum
and compares it with the value stored at EEPROM
address 0x0F. If computed and stored address match
normal operation begins. Otherwise, iC-TW3 asserts
an error condition and pin NERR is pulled low.
It is the user’s responsibility to store the correct check-
sum in the EEPROM during production programming.
CHECKSUM(7:0) Adr 0x0F; Bit 7:0
R/W
Code
Function
...
Checksum of EEPROM contents
Table 5: Checksum
EEPROM Register Map
The 14 bytes of device configuration data are followed
by a minimum of 2 to a maximum of 16 lock-up-table
blocks (LUT). The LUT block size is 6 bytes each and
the final block is indicated by its breakpoint value of
255.
Thus, a minimum of 28 bytes are read with 2 active
LUT blocks and 112 bytes are read with 16 active LUT
blocks during the configuration phase. Note that the
checksum is only calculated up and including the last
LUT block. The last LUT block ist indicated by a break-
point value of 255. Further descriptions on LUTs are
given in section "Temperature Compensation" on page
21.
Note that the EEPROM address space maps to the
1-wire address 128. Accessing EEPROM address 0 is
therefore equivalent to accessing memory location 128
via the 1-wire interface (see page 12).
EEPROM
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
EEPROM
Address
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
.
.
.
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
Description
<reserved>
Config. 1
Config. 2
Config. 3
Config. 4
Temp. Sensing
Config. Index
Coarse Gain
COFSA
COFSB
DGAINA
DGAINB
DOFSA
DOFSB
Test 1
CHECKSUM
Description
Breakpoint 0
GAINA
GAINB
OFSA
OFSB
OFSZ
Breakpoint 1 (255)
GAINA
GAINB
OFSA
OFSB
OFSZ
.
.
.
Breakpoint 255
GAINA
GAINB
OFSA
OFSB
OFSZ
Corresponding
Configuration Register
-
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
LUT Block Number
0
0
0
0
0
0
1
1
1
1
1
1
.
.
.
15
15
15
15
15
15
Table 6: EEPROM register map