HYMD564M646A8-J Datasheet, PDF (9/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD564M646A(L)8-J/K/H
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-J -K -H
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle ; address and control inputs
changing once per clock cycle
1120 960 960 mA
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst Length =2;
tRC=tRC(min); tCK=tCK(min); address and control
1440 1200 1200 mA
inputs changing once per clock cycle
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=
tCK(min)
80
80
80 mA
Idle Standby Current
IDD2N Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
280
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
280
mA
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref for
DQ, DQS and DM
200
mA
Active Power Down
Standby Current
One bank active ; Power down mode; CKE=Low,
IDD3P _tCK=tCK(min)
96
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
Active Standby Current
IDD3N
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
360 320 320 mA
other control inputs changing once per clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
2000 1680 1680
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM, and DQS inputs
changing twice per clock cycle
2000 1680 1680 mA
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
2240 2080 2080
Self Refresh Current
CKE=<0.2V; External clock on; tCK
IDD6 _=tCK(min)
Normal
Low Power
40
mA
20
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
3680
3040
3040
mA
Random Read Current
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
IDD7A mA, 100% DQ, DM and DQS inputs changing twice 3680 3040 3040 mA
per clock cycle; 100% addresses changing once per
clock cycle
Rev. 0.2 / Apr. 2004
9