HYMD564M646A8-J Datasheet, PDF (16/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0 Number of Bytes written into serial memory at module
manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15 Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=2.0(tCK)
24 DDR SDRAM access time from clock at CL=2.0(tAC)
25 DDR SDRAM cycle time at CL=1.5(tCK)
26 DDR SDRAM access time from clock at CL=1.5(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh Time (tRC)
42
Minimum auto-refresh to active / auto-refresh
command period (tRFC)
43 Maximum cycle time (tCK max)
44 Maximum DQS-DQ skew time (tDQSQ)
45 Maximum read data hold skew factor (tQHS)
46~61 Superset Information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
HYMD564M646A(L)8-J/K/H
Bin Sort : J(DDR333@CL=2.5), K(DDR266A@CL=2), H(DDR266B@CL=2.5)
Function Supported
J
K
H
128 Bytes
256 Bytes
DDR SDRAM
13
11
1Bank
64 Bits
-
SSTL 2.5V
6.0ns
7.5ns
7.5ns
+/-0.7ns +/-0.75ns +/-0.75ns
Non-ECC
7.8us & Self refresh
x8
N/A
1 CLK
2,4,8
4 Banks
2, 2.5
0
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
7.5ns
7.5ns
10ns
+/-0.7ns +/-0.75ns +/-0.75ns
-
-
18ns
20ns
20ns
12ns
15ns
15ns
18ns
20ns
20ns
42ns
45ns
45ns
512MB
0.75ns
0.9ns
0.9ns
0.75ns
0.9ns
0.9ns
0.45ns
0.5ns
0.5ns
0.45ns
0.5ns
0.5ns
Undefined
60ns
65ns
65ns
72ns
75ns
75ns
12ns
12ns
12ns
0.45ns
0.5ns
0.5ns
0.55ns 0.75ns 0.75ns
Undefined
Initial release
-
Hexa Value
J
K
H
80h
08h
07h
0Dh
0Bh
01h
40h
00h
04h
60h
75h
75h
70h
75h
75h
00h
82h
08h
00h
01h
0Eh
04h
0Ch
01h
02h
20h
C0h
75h
75h
A0h
70h
75h
75h
00h
00h
48h
50h
50h
30h
3Ch
3Ch
48h
50h
50h
2Ah
2Dh
2Dh
80h
75h
90h
90h
75h
90h
90h
45h
50h
50h
45h
50h
50h
00h
3Ch
41h
41h
48h
4Bh
4Bh
30h
30h
30h
2Dh
32h
32h
55h
75h
75h
00h
00h
41h
F8h
23h
Note
1
1
2
2
Rev. 0.2 / Apr. 2004
16