HYMD564M646A8-J Datasheet, PDF (7/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

CAPACITANCE (TA=25^oC, f=100MHz )
HYMD564M646A(L)8-J/K/H
Parameter
Pin
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Data Input / Output Capacitance
A0 ~ A12, BA0, BA1
/RAS, /CAS, /WE
CKE0, CKE1
/CS0, /CS1
CK0, /CK0, CK1, /CK1
DM0 ~ DM7
DQ0 ~ DQ63, DQS0 ~ DQS7
Symbol Min
CIN1
36
CIN2
36
CIN3
36
CIN4
36
CIN5
18
CIN6
7
CIO1
7
Max
48
48
48
48
27
12
12
Unit
pF
pF
pF
pF
pF
pF
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Output
VTT
RT=50Ω
Zo=50Ω
CL=30pF
VREF
Rev. 0.2 / Apr. 2004
7