HYMD525G726AS4-M Datasheet, PDF (9/17 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD525G726A(L)S4M-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle ; address and control inputs
changing once per clock cycle
3620 3440 3440 3080 mA
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst Length
=2; tRC=tRC(min); tCK=tCK(min); address and
4160
control inputs changing once per clock cycle
3980
3800 mA
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=
tCK(min)
1010
mA
Idle Standby Current
IDD2N
Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and
DM
1910
mA
/CS=High, All banks idle; tCK=tCK(min); CKE=
Idle Standby Current IDD2F High; address and control inputs changing once per
1910
mA
clock cycle. VIN=VREF for DQ, DQS and DM
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref
for DQ, DQS and DM
1730
mA
Active Power Down
Standby Current
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
1082
mA
/CS=HIGH; CKE=HIGH; One bank; Active-
Active Standby
Current
IDD3N
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
2000
mA
clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
4880
4340
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM, and DQS
inputs changing twice per clock cycle
4880
4340 mA
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
5660
5300
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
530
mA
440
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
8120
6680 mA
Random Read
Current
IDD7A
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
tRCD=3, IOUT=0 mA, 100% DQ, DM and DQS
inputs changing twice per clock cycle; 100%
addresses changing once per clock cycle
8120
6680 mA
Rev. 0.3 / Apr. 2004
9