HYMD525G726AS4-M Datasheet, PDF (16/17 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD525G726A(L)S4M-M/K/H/L
SERIAL PRESENCE DETECT
Bin Sort : M(DDR266 2-2-2@CL=2), K(DDR266A@CL=2)
H(DDR266B@CL=2.5), L(DDR200@CL=2)
Byte#
Function Description
Function Supported
M
K
H
L
M
Number of Bytes written into serial memory at mod-
0 ule
manufacturer
128 Bytes
1 Total number of Bytes in SPD device
256 Bytes
2 Fundamental memory type
DDR SDRAM
3 Number of row address on this assembly
13
4 Number of column address on this assembly
12
5 Number of physical banks on DIMM
2Bank
6 Module data width
72 Bits
7 Module data width (continued)
-
8 Module voltage Interface levels(VDDQ)
SSTL 2.5V
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
7.5ns
7.5ns
7.5ns
8ns
75h
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
+/-
+/-
+/- +/-0.8ns 75h
0.75ns 0.75ns 0.75ns
11 Module configuration type
ECC
12 Refresh rate and type
7.8us & Self refresh
13 Primary DDR SDRAM width
x4
14 Error checking DDR SDRAM data width
x4
15
Minimum clock delay for back-to-back random column
address(tCCD)
1 CLK
16 Burst lengths supported
2,4,8
17 Number of banks on each DDR SDRAM
4 Banks
18 CAS latency supported
2, 2.5
19 CS latency
0
20 WE latency
1
21 DDR SDRAM module attributes
Registered, PLL
22 DDR SDRAM device attributes : General
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
23 DDR SDRAM cycle time at CL=2.0(tCK)
7.5ns 7.5ns
10ns
10ns
75h
24 DDR SDRAM access time from clock at CL=2.0(tAC)
+/-
+/-
+/- +/-0.8ns 75h
0.75ns 0.75ns 0.75ns
25 DDR SDRAM cycle time at CL=1.5(tCK)
-
26 DDR SDRAM access time from clock at CL=1.5(tAC)
-
27 Minimum row precharge time(tRP)
15ns
20ns
20ns
20ns
3Ch
28 Minimum row activate to row active delay(tRRD)
15ns
15ns
15ns
15ns
3Ch
29 Minimum RAS to CAS delay(tRCD)
15ns
20ns
20ns
20ns
3Ch
30 Minimum active to precharge time(tRAS)
45ns
45ns
45ns
50ns
2Dh
31 Module row density
1GB
32 Command and address signal input setup time(tIS)
0.9ns 0.9ns 0.9ns 1.1ns
90h
33 Command and address signal input hold time(tIH)
0.9ns 0.9ns
0.9ns
1.1ns
90h
34 Data signal input setup time(tDS)
0.5ns
0.5ns 0.5ns
0.6ns
50h
35 Data signal input hold time(tDH)
0.5ns
0.5ns 0.5ns
0.6ns
50h
36~40 Reserved for VCSDRAM
Undefined
41 Minimum active / auto-refresh time ( tRC)
60ns
65ns
65ns
70ns
3Ch
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
75ns
75ns
75ns
80ns
4Bh
43 Maximum cycle time (tCK max)
12ns
12ns
12ns
12ns
30h
44 Maximim DQS-DQ skew time(tDQSQ)
0.5ns 0.5ns 0.5ns
0.6ns
32h
45 Maximum read data hold skew factor(tQHS)
46~61 Superset information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
0.75ns 0.75ns 0.75ns 0.75ns 75h
Undefined
Initial release
-
5Eh
Hexa Value
K
H
Note
L
80h
08h
07h
0Dh
1
0Ch
1
02h
48h
00h
04h
75h 75h 80h
2
75h 75h 80h
2
02h
82h
04h
04h
01h
0Eh
04h
0Ch
01h
02h
26h
C0h
75h A0h A0h
2
75h 75h 80h
2
00h
2
00h
2
50h 50h 50h
3Ch 3Ch 3Ch
50h 50h 50h
2Dh 2Dh 32h
01h
90h 90h B0h
90h 90h B0h
50h 50h 60h
50h 50h 60h
00h
41h 41h 46h
4Bh 4Bh 50h
30h 30h 30h
32h 32h 3Ch
75h 75h 75h
00h
00h
8Bh B6h 50h
Rev. 0.3 / Apr. 2004
16