HYMD525G726AS4-M Datasheet, PDF (10/17 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD525G726A(L)S4M-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-M(DDR266 2-2-2) -K(DDR266A) -H(DDR266B)
Symbol
Min
Max Min Max Min Max
-L(DDR200)
Unit Note
Min Max
Row Cycle Time
tRC
60
-
65
-
65
-
70
- ns
Auto Refresh Row Cycle Time
tRFC
75
-
75
-
75
-
80
- ns
Row Active Time
tRAS
45
120K 45 120K 45 120K
50
120K ns
Active to Read with Auto Precharge
Delay
tRAP
tRCD or
tRP min
-
tRCD or
tRP min
-
tRCD or
tRP min
-
tRCD or
tRP min
- ns 16
Row Address to Column Address
Delay
tRCD
15
-
20
-
20
-
20
- ns
Row Active to Row Active Delay
tRRD
15
-
15
-
15
-
15
- ns
Column Address to Column Address
Delay
tCCD
1
-
1
-
1
-
1
- CK
Row Precharge Time
tRP
15
-
20
-
20
-
20
- ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
- ns
Write to Read Command Delay
tWTR
1
-
1
-
1
-
1
- CK
Auto Precharge Write
Recovery+Precharge Time
tDAL
2+(tRP/
tCK)
-
(tWR/tCK)
5
-
5
-
+
- CK 15
(tRP/tCK)
System Clock Cycle
Time
CL = 2.5
CL = 2
tCK
7.5
7.5
12
7.5 12 7.5 12
12
7.5
12
10
12
8
10
12 ns
12 ns
Clock High Level Width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge Skew tAC
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns
DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns
DQS-Out edge to Data-Out edge
Skew
tDQSQ
-
0.5
-
0.5
-
0.5
-
0.6 ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
- ns 1, 10
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
- ns 1,9
Data Hold Skew Factor
tQHS
-
0.75
-
0.75
-
0.75
-
0.75 ns 10
Valid Data Output Window
tDV
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
Data-out high-impedance window
from CK, /CK
tHZ
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8
0.8 ns
Data-out low-impedance window
from CK, /CK
tLZ
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8
0.8 ns
Input Setup Time (fast slew rate)
tIS
0.9
-
0.9
-
0.9
-
1.1
-
ns
2,3,5
,6
Input Hold Time (fast slew rate)
tIH
0.9
-
0.9
-
0.9
-
1.1
-
ns
2,3,5
,6
Input Setup Time (slow slew rate)
tIS
1.0
-
1.0
-
1.0
-
1.1
-
ns
2,4,5
,6
Input Hold Time (slow slew rate)
tIH
1.0
-
1.0
-
1.0
-
1.1
-
ns
2,4,5
,6
Input Pulse Width
tIPW
2.2
-
2.2
-
2.2
-
2.5
- ns 6
Rev. 0.3 / Apr. 2004
10