HYMD264M646BLF8-D43 Datasheet, PDF (9/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD264M646B(L)F8-D43/D4
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Operating Current
Operating Current
Precharge Power
Down Standby
Current
Idle Standby Current
Active Power Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current -
Four Bank Operation
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle
; address and control inputs changing once
per clock cycle
IDD1
One bank; Active - Read - Precharge;
Burst Length=4; tRC=tRC(min);
tCK=tCK(min); address and control inputs
changing once per clock cycle
IDD2P
All banks idle; Power down - mode;
CKE=Low, tCK=tCK(min)
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF
for DQ, DQS and DM
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max);
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle
IDD4R
Burst=2; Reads; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
IDD6
CKE=<0.2V; External clock
on; tCK =tCK(min)
Normal
Low Power
IDD7
Four bank interleaving with BL=4 Refer to
the following page for detailed test
condition
Speed
D43
(3-3-3)
D4
(3-4-4)
1120
1120
160
560
240
600
1600
1760
1600
48
24
2400
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.2 / Apr. 2004
9