HYMD264M646BLF8-D43 Datasheet, PDF (16/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0
Number of Bytes written into serial memory at module
manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=X(tCK)
10 DDR SDRAM access time from clock at CL=X (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=X-0.5(tCK)
24 DDR SDRAM access time from clock at CL=X-0.5(tAC)
25 DDR SDRAM cycle time at CL=X-1(tCK)
26 DDR SDRAM access time from clock at CL=X-1(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh time ( tRC)
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
43 Maximum cycle time (tCK max)
44 Maximim DQS-DQ skew time(tDQSQ)
45 Maximum read data hold skew factor(tQHS)
46~61 Superset information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
HYMD264M646B(L)F8-D43/D4
Bin Sort :D43(DDR400 3-3-3), D4(DDR400(3-4-4)
Function Supported
D43
D4
Hexa Value
D43
D4
Note
128 Bytes
80h
256 Bytes
DDR SDRAM
13
10
2Banks
64 Bits
-
SSTL 2.5V
5.0ns
5.0ns
+/-0.7ns
Non-ECC
7.8us & Self refresh
x8
N/A
08h
07h
0Dh
1
0Ah
1
02h
40h
00h
04h
50h
50h
2
70h
2
00h
82h
08h
00h
1 CLK
01h
2,4,8
0Eh
4 Banks
04h
2, 2.5, 3
2, 2.5, 3
1Ch
1Ch
0
01h
1
02h
Differential Clock Input
20h
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
C0h
tRAS Lock Out
6ns
6ns
60h
60h
2
+/-0.7ns
+/-0.7ns
70h
70h
2
7.5ns
7.5ns
75h
75h
2
+/-0.75ns
+/-0.75ns
75h
75h
2
15ns
18ns
3Ch
48h
10ns
10ns
28h
28h
15ns
18ns
3Ch
48h
40ns
40ns
28h
28h
256MB
40h
0.60ns
0.60ns
60h
60h
0.60ns
0.60ns
60h
60h
0.40ns
0.40ns
40h
40h
0.40ns
0.40ns
40h
40h
Undefined
00h
55ns
58ns
37h
3Ah
70ns
70ns
46h
46h
10ns
10ns
0.40ns
0.40ns
0.50ns
0.50ns
Undefined
inital release
-
28h
28h
28h
28h
50h
50h
00h
00h
67h
80h
Rev. 0.2 / Apr. 2004
16