HYMD232726B8J-J Datasheet, PDF (9/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD232726B(L)8-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
DDR266(2-2-2)
Symbol
Min Max
DDR266A
Min Max
DDR266B
Min Max
DDR200
Unit Note
Min Max
Row Cycle Time
tRC
60
-
65
-
65
-
70
- ns
Auto Refresh Row Cycle Time
tRFC
75
-
75
-
75
-
80
- ns
Row Active Time
tRAS
45
120K
45
120K 45 120K
50
120K ns
Active to Read with Auto
Precharge Delay
tRAP
15
-
20
-
20
-
20
- ns 16
Row Address to Column Address
Delay
tRCD
15
-
20
-
20
-
20
- ns
Row Active to Row Active Delay tRRD
15
-
15
-
15
-
15
- ns
Column Address to Column
Address Delay
tCCD
1
-
1
-
1
-
1
- CK
Row Precharge Time
tRP
15
-
20
-
20
-
20
- ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
- ns
Write to Read Command Delay tWTR
1
-
1
-
1
-
1
- CK
Auto Precharge Write Recovery
+ Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
-
+
-
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
-
CK 15
System Clock
Cycle Time
CL = 2.5
7.5
12
7.5
12
7.5
12
8.0
12 ns
tCK
CL = 2
7.5
12
7.5
12
10
12
10
12 ns
Clock High Level Width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge
Skew
tAC
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8
0.8 ns
DQS-Out edge to Clock edge
Skew
tDQSCK -0.75
0.75
-0.75 0.75 -0.75 0.75
-0.8
0.8 ns
DQS-Out edge to Data-Out edge
Skew
tDQSQ
-
0.5
-
0.5
-
0.5
-
0.6 ns
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
- ns 1, 10
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns 1,9
Data Hold Skew Factor
tQHS
-
0.75
-
0.75
-
0.75
-
0.75 ns 10
Valid Data Output Window
tDV
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
Data-out high-impedance
window from CK, /CK
tHZ
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8
0.8 ns 17
Data-out low-impedance window
from CK, /CK
tLZ
-0.75 0.75 -0.75 0.75 -0.75 0.75 -0.8
0.8 ns 17
Rev. 0.1/Oct. 02
9