HYMD232726B8J-J Datasheet, PDF (15/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD232726B(L)8-M/K/H/L
SERIAL PRESENCE DETECT
Byte#
Function Description
0
Number of Bytes written into serial memory at module
manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 _{DDR SDRAM device attributes : General}
23 DDR SDRAM cycle time at CL=2.0(tCK)
24 DDR SDRAM access time from clock at CL=2.0(tAC)
25 DDR SDRAM cycle time at CL=1.5(tCK)
26 DDR SDRAM access time from clock at CL=1.5(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh time ( tRC)
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
43 Maximum cycle time (tCK max)
44 Maximim DQS-DQ skew time(tDQSQ)
45 Maximum read data hold skew factor(tQHS)
46~61 Superset information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
Bin Sort :M(DDR266(2-2-2),K(DDR266A@CL=2)
H(DDR266B@CL=2.5),L(DDR200@CL=2)
Function Supported
M
K
H
L
Hexa Value
Note
M
K
H
L
128 Bytes
80h
256 Bytes
08h
DDR SDRAM
07h
13
0Dh
1
10
0Ah
1
1Bank
01h
72 Bits
48h
-
00h
SSTL 2.5V
04h
7.5ns 7.5ns 7.5ns 8.0ns 75h 75h 75h 80h
2
+/-0.75ns
+/-0.8ns 75h 75h 75h 80h
2
ECC
02h
7.8us & Self refresh
82h
x8
08h
x8
08h
1 CLK
01h
2,4,8
0Eh
4 Banks
04h
2, 2.5
0Ch
0
01h
1
02h
Differential Clock Input
20h
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
C0h
tRAS Lock Out
7.5ns 7.5ns 10ns 10ns 75h 75h A0h A0h
2
+/-0.75ns
+/-0.8ns 75h 75h 75h 80h
2
-
00h
2
-
00h
2
15ns 20ns 20ns 20ns 3Ch 50h 50h 50h
15ns 15ns 15ns 15ns 3Ch 3Ch 3Ch 3Ch
15ns 20ns 20ns 20ns 3Ch 50h 50h 50h
45ns 45ns 45ns 50ns 2Dh 2Dh 2Dh 32h
256MB
40h
0.9ns 0.9ns 0.9ns 1.1ns 90h 90h 90h B0h
0.9ns 0.9ns 0.9ns 1.1ns 90h 90h 90h B0h
0.5ns 0.5ns 0.5ns 0.6ns 50h 50h 50h 60h
0.5ns 0.5ns 0.5ns 0.6ns 50h 50h 50h 60h
Undefined
00h
60ns 65ns 65ns 70ns 3Ch 41h 41h 46h
75ns 75ns 75ns 80ns 4Bh 4Bh 4Bh 50h
12ns 12ns 12ns 12ns 30h 30h 30h 30h
0.5ns 0.5ns 0.5ns 0.6ns 32h 32h 32h 3Ch
0.75ns 0.75ns 0.75ns 0.75ns 75h 75h 75h 75h
Undefined
00h
Initial release
00h
-
9Ch C9h F4h 8Eh
Rev. 0.1/Oct. 02
15