HYMD232726B8J-J Datasheet, PDF (12/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD232726B(L)8-M/K/H/L
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1 CKEn
/CS
/RAS /CAS
/WE
ADDR
A10/
AP
BA Note
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
Device Deselect
No Operation
H
X
X
X
H
X
X
1
L
H
H
H
Bank Active
H
X
L
L
H
H
RA
V
1
Read
Read with Autoprecharge
L
1
H
X
L
H
L
H
CA
V
H
1,3
Write
Write with Autoprecharge
L
1
H
X
L
H
L
L
CA
V
H
1,4
Precharge All Banks
Precharge selected Bank
H
X
1,5
H
X
L
L
H
L
X
L
V
1
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Entry
H
L
L
L
L
H
1
Self Refresh
H
X
X
X
X
Exit
L
H
1
L
H
H
H
H
X
X
X
1
Entry
H
L
Precharge
L
H
H
H
1
Power Down
X
Mode
H
X
X
X
1
Exit
L
H
L
H
H
H
1
H
X
X
X
1
Active Power
Down Mode
Entry
H
L
L
V
V
V
X
1
Exit
L
H
X
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
Rev. 0.1/Oct. 02
12