HYMD216M646CL6-D43 Datasheet, PDF (9/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD216M646C(L)6-D43/D4/J
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Operating Current
Operating Current
Precharge Power Down
Standby Current
Idle Standby Current
Active Power Down
Standby Current
Idle Quiet Standby
Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current -
Four Bank Operation
Random Read Current
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD2Q
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
IDD7A
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min);
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF
for DQ, DQS and DM
One bank active ; Power down mode;
CKE=Low, tCK=tCK(min)
/CS>=Vih(min); All banks idle;
CKE>=Vih(min); Addresses and other
control inputs stable, Vin=Vref for DQ, DQS
and DM
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock
cycle
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B
at 133Mhz; distributed refresh
CKE=<0.2V; External clock on; ^Normal
tCK =tCK(min)
Low Power
Four bank interleaving with BL=4 Refer to
the following page for detailed test condition
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
tRCD=3, IOUT=0 mA, 100% DQ, DM and
DQS inputs changing twice per clock cycle;
100% addresses changing once per clock
cycle
-D43
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Speed
-D4
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit Note
-J
420
mA
600
mA
80
mA
200
mA
100
mA
TBD mA
240
mA
1160
mA
1160
920
12
mA
6
mA
1340 mA
TBD mA
Rev. 0.1 / Apr. 2003
9