HYMD216M646CL6-D43 Datasheet, PDF (12/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD216M646C(L)6-D43/D4/J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400 (D43)
Min
Max
DDR400 (D4)
Unit
Min
Max
Row Cycle Time
tRC
55
-
58
-
ns
Auto Refresh Row Cycle Time
tRFC
70
-
70
-
ns
Row Active Time
tRAS
40
70K
40
70K
ns
Active to Read with Auto Precharge Delay
tRAP
tRCD or
tRAS(min)
-
tRCD or
tRAS(min)
-
ns
Row Address to Column Address Delay
tRCD
15
-
18
-
ns
Row Active to Row Active Delay
tRRD
10
-
10
-
ns
Column Address to Column Address Delay
tCCD
1
-
1
-
CK
Row Precharge Time
tRP
15
-
18
-
ns
Write Recovery Time
tWR
15
-
15
-
ns
Write to Read Command Delay
tWTR
2
-
2
-
CK
(tWR/tCK)
(tWR/tCK)
Auto Precharge Write Recovery + Precharge Time tDAL
+
-
+
-
CK
(tRP/tCK)
(tRP/tCK)
System Clock Cycle Time
CL = 3
tCK
5
10
5
10
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Clock edge Skew
tDQSCK -0.55
0.55
-0.55
0.55
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.4
ns
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHP
-tQHS
-
ns
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
Data Hold Skew Factor
tQHS
-
0.5
-
0.5
ns
Data-out high-impedance window from CK, /CK
tHZ
tAC(Max)
tAC(Max) ns
Data-out low-impedance window from CK, /CK
tLZ
tAC(min) tAC(Max) tAC(min) tAC(Max) ns
Input Setup Time (fast slew rate)
tIS
0.6
-
0.6
-
ns
Input Hold Time (fast slew rate)
tIH
0.6
-
0.6
-
ns
Input Setup Time (slow slew rate)
tIS
0.7
-
0.7
-
ns
Input Hold Time (slow slew rate)
tIH
0.7
-
0.7
-
ns
Note
16
15
1, 10
1,9
10
17
17
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
Rev. 0.1 / Apr. 2003
12