HYMD216M646CL6-D43 Datasheet, PDF (2/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

DESCRIPTION
16Mx64 bits
Unbuffered DDR SO-DIMM
HYMD216M646C(L)6-D43/D4/J
Hynix HYMD216M646C(L)6-D43/D4/J series is unbuffered 200-pin double data rate Synchronous DRAM Small Out-
line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 16Mx64 high-speed memoryarrays. Hynix
HYMD216M646C(L)6-D43/D4/J series consists of four 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin
glass-epoxy substrate. Hynix HYMD216M646C(L)6-D43/D4/J series provide a high performance 8-byte interface in
67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD216M646C(L)6-D43/D4/J series is designed for high speed of up to 200MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD216M646C(L)6-D43/D4/J series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 128MB (16M x 64) Unbuffered DDR SO-DIMM
based on 16Mx16 DDR SDRAM
both rising and falling edges of the clock
• Data inputs on DQS centers when write (centered
• JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
• 2.6V +/- 0.1V VDD and VDDQ Power supply
(2.5V +/- 0.2V for DDR333)
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz/166MHz/200MHz
DQ)
• Data strobes synchronized with output data for read
and input data for write
• Programmable CAS Latency 2 / 2.5 / 3 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• tRAS Lock-out function supported
• All addresses and control inputs except Data, Data
• Internal four bank operations with single pulsed RAS
strobes and Data masks latched on the rising edges _{• Auto refresh and self refresh supported}
of the clock
• 8192 refresh cycles / 64ms
• Data(DQ), Data strobes and Write masks latched on
ORDERING INFORMATION
Part No.
HYMD216M646C(L)6-D43
HYMD216M646C(L)6-D4
HYMD216M646C(L)6-J
Power Supply
VDD=2.6V
VDDQ=2.6V
VDD=2.5V
VDDQ=2.5V
Clock Frequency
200MHz (*DDR400)
200MHz (*DDR400)
166MHz (*DDR333)
Interface
Form Factor
SSTL_2
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 1mm
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Apr. 2003
2