HYMD264646C8-M Datasheet, PDF (8/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD264646C(L)8-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
1320 1160 1160 1120 mA
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle
1680 1440 1440 1360 mA
Precharge Power Down
Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
320
mA
Idle Standby Current
/CS=High, All banks idle ; tCK=tCK(min);
IDD2F
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF for
800
640
640
560
mA
DQ, DQS and DM
Active Power Down
Standby Current
One bank active; Power down mode;
IDD3P _{CKE=Low, tCK=tCK(min)}
400
mA
Active Standby Current
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tR=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per 960 800 800 800 mA
clock cycle; Address and other control inputs
changing once per clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
2800
2400
2400
1920
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM, and DQS inputs
changing twice per clock cycle
2800 2400 2400 1920 ^mA
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for PC200 at
100Mhz, 10*tCK for PC266A & PC266B at
133Mhz; distributed refresh
2320 2080 2080 1960
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; ^Normal
tCK =tCK(min)
Low Power
48
24
mA
mA
Operating Current - Four
Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to
the following page for detailed test condition
3000
2840
2840
2640
mA
Rev. 0.1 / Mar. 2003
8