HY57V64820HG Datasheet, PDF (8/11 Pages) Hynix Semiconductor – 4 Banks x 2M x 8Bit Synchronous DRAM

HY57V64820HG
AC CHARACTERISTICS II
Parameter
Symbol
-6
Min Max
-7
Min Max
-K
Min Max
-H
Min Max
-8
Min Max
-P
Min Max
-S
Min Max
Unit
Note
Operation tRC
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
RAS Cycle Time
Auto
Refresh
tRRC
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
RAS to CAS Delay
tRCD
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS Active Time
tRAS
42 100K 42 120K 45 120K 45 120K 48 120K 50 120K 50 120K ns
RAS Precharge Time
tRP
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS to RAS Bank Active Delay tRRD
12
-
14
-
15
-
15
-
16
-
20
-
20
-
ns
CAS to CAS Delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to Data-In
Delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge
Command
tDPL
2
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Data-In to Active Command tDAL
5
-
4
-
4
-
4
-
4
-
3
-
3
-
CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
tMRD
2
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Precharge to
CAS
Latency = 3
tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
Data Output Hi-Z
CAS
Latency = 2
tPROZ2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.5/Sep. 02
8