HY57V64820HG Datasheet, PDF (6/11 Pages) Hynix Semiconductor – 4 Banks x 2M x 8Bit Synchronous DRAM

HY57V64820HG
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-6
-7
-K
-H
-8 -P/S
Operating Current
IDD1
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
90
85
85
85
85
80 mA
1
Precharge Standby Current
in Power Down Mode
IDD2P
IDD2PS
CKE ≤ VIL(max), tCK = min
CKE ≤ VIL(max), tCK = ∞
2
mA
2
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
IDD2N
Input signals are changed one time during
15
mA
Precharge Standby Current
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
in Non Power Down Mode
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
12
mA
Active Standby Current
in Power Down Mode
IDD3P
IDD3PS
CKE ≤ VIL(max), tCK = min
CKE ≤ VIL(max), tCK = ∞
6
mA
5
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
IDD3N
Input signals are changed one time during
30
mA
Active Standby Current
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
in Non Power Down Mode
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
20
mA
Burst Mode Operating Current IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
CL=3
150 150 150 150 130 120 mA
1
CL=2
NA NA
120
mA
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), All banks active
160
mA
2
Self Refresh Current
IDD6
CKE ≤ 0.2V
1
mA
3
400
uA
4
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V64820HGT-7/K/H/8/P/S
4.HY57V64820HGLT-7/K/H/8/P/S
Rev. 0.5/Sep. 02
6