HY57V64820HG Datasheet, PDF (7/11 Pages) Hynix Semiconductor – 4 Banks x 2M x 8Bit Synchronous DRAM

HY57V64820HG
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
-6
-7
-K
-H
-8
-P
-S
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
System clock
cycle time
CAS
Latency = 3
CAS
Latency = 2
tCK3
tCK2
6
7
7.5
7.5
8
10
10
ns
1000
1000
1000
1000
1000
1000
1000
10
10
7.5
10
10
10
12
ns
Clock high pulse width
tCHW 2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW 2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Access time
CAS
Latency = 3
tAC3
-
5.4
-
5.4
-
5.4
from clock
CAS
Latency = 2
tAC2
-
6
-
6
-
5.4
5.4
-
6
6
-
6
ns
2
6
-
6
-
6
-
8
ns
Data-out hold time
tOH
2.7
-
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address hold time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS 1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE hold time
tCKH 0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command hold time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-
time
tOLZ
1
-
1.5
-
1.5
-
1.5
-
1
-
1
-
2
-
ns
CLK to data
CAS
Latency = 3
tOHZ3
ns
output in high
5.4
5.4
5.4
5.4
6
6
6
Z-time
CAS
Latency = 2
tOHZ2
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.5/Sep. 02
7