HY57V641620HG-I Datasheet, PDF (8/12 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

HY57V641620HG
AC CHARACTERISTICS II
Parameter
Symbo
-5I
l
Min Max
-55I
Min Max
-6I
-7I
Min Max Min Max
-KI
Min Max
-HI
-8I
-PI
Min Max Min Max Min Max
-SI
Min Max
Unit
Note
Operation
tRC
RAS Cycle
55 - 55 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns
Time
Auto Refresh tRRC 60 - 60 - 60 - 62 - 65 - 65 - 68 - 70 - 70 - ns
RAS to CAS Delay
tRCD 15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns
RAS Active Time
tRAS
38.5 100K 38.5 100K 42
100
K
42 120K
45 120K 45 120K 48
100
K
50 120K 50
120K
ns
RAS Precharge Time
tRP
15 - 16.5 - 18 - 20 - 15 - 20 - 20 - 20 - 20 - ns
RAS to RAS Bank Active
Delay
tRRD 10 - 11 - 12 - 14 - 15 - 15 - 16 - 20 - 20 - ns
CAS to CAS Delay
tCCD
1
-
1
-
1-
1
-
1
-
1
-
1-
1
-
1
- CLK
Write Command to Data-In
Delay
tWTL
0
-
0
-
0-
0
-
0
-
0
-
0-
0
-
0
- CLK
Data-In to Precharge
Command
tDPL
2
-
2
- 2- 2
-
2
-
2
- 2- 2
-
2
- CLK
Data-In to Active Command tDAL
5
-
5
- 5- 4
-
4
-
4
- 5- 3
-
3
- CLK
DQM to Data-Out Hi-Z
tDQZ
2
-
2
-
2-
2
-
2
-
2
-
2-
2
-
2
- CLK
DQM to Data-In Mask
tDQM 0
-
0
-
0-
0
-
0
-
0
-
0-
0
-
0
- CLK
MRS to New Command
tMRD
2
-
2
-
2-
1
-
1
-
1
-
2-
1
-
1
- CLK
CAS Latency tPROZ
Precharge to = 3
3
3
-
3
-
3-
3
-
3
-
3
-
3-
3
-
3
- CLK
Data Output
Hi-Z
CAS Latency tPROZ
=2
2
2
-
2
-
2-
2
-
2
-
2
-
2-
2
-
2
- CLK
Power Down Exit Time
tPDE
1
-
1
-
1-
1
-
1
-
1
-
1-
1
-
1
- CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1-
1
-
1
-
1
-
1-
1
-
1
- CLK 1
Refresh Time
tREF
- 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 - 64 ms
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 1.0/Jan. 02
8