HMS87C13042A Datasheet, PDF (71/88 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C130XA/120XA/110XA
19. POWER FAIL PROCESSOR
The HMS87C1X0XA has an on-chip power fail detection
circuitry to immunize against power noise. A Power Fail
Detector Register, PFDR can enable (if clear/pro-
grammed) or disable (if set) the Power fail Detect circuitry.
If V_DD falls below 2.4~2.6V(or 1.6~1.8V) range for longer
than 50 nS, the Power fail situation may reset MCU or halt
the system clock according to PFS bit of PFDR. And pow-
er fail detect level is selectable by programming the bit
PFDLEVEL of CONFIG register when program the OTP.
As below PFDR register is not implemented on the in-cir-
cuit emulator, user can not experiment with it. Therefore,
after final development of user program, this function may
be experimented.
Note: Power fail detect level is decided by setting the bit
PFDLEVEL of CONFIG register (refer to Figure 20-
1.
Power Noise
PFDIS
PFDOPR
PFDM
Power
Fail
Detection
Circuit
PFS
to RESET circuit
System clock freeze
PFDR
Power Fail Detector Register
-
-
-
Reserved
-
PFDOPR PFDIS PFDM PFS
ADDRESS : EFH
RESET VALUE : ----0100
Power Fail Status
0 : Normal Operate
1 : This bit force to “1” when
Power fail was detected
Operation Mode
0 : System Clock Freeze during power fail
1 : MCU will be reset during power fail
Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
PFD Operation Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
But can read PFS
Figure 19-1 Power Fail Detector
68
Apr. 2001 ver 1.0