HMS87C13042A Datasheet, PDF(58/88 Page) Hynix Semiconductor

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HMS87C13042A Datasheet, PDF (58/88 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

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HMS87C130XA/120XA/110XA

The interrupts are controlled by the interrupt master enable

flag I-flag (bit 2 of PSW), the interrupt enable register

(IENH, IENL) and the interrupt request flags (in IRQH,

IRQL) except Power-on reset and software BRK interrupt.

Interrupt enable registers are shown in Figure 15-2. These

registers are composed of interrupt enable flags of each in-

terrupt source, these flags determines whether an interrupt

will be accepted or not. When enable flag is â0â, a corre-

sponding interrupt source is prohibited. Note that PSW

contains also a master enable bit, I-flag, which disables all

interrupts at once.

Reset/Interrupt Symbol Priority Vector Addr.

Hardware Reset RESET

External Interrupt 0 INT0

External Interrupt 1 INT1

Timer 0

Timer 1

A/D Converter

A/D C

Watch Dog Timer WDT

Basic Interval Timer BIT

Table 15-1 Interrupt Priority

FFFEH

FFFAH

FFF8H

FFF6H

FFF4H

FFEAH

FFE8H

FFE6H

Interrupt Enable Register High

IENH

ADDRESS : E2H

INT0E INT1E

T0E

T1E

RESET VALUE : 0000----

Interrupt Enable Register Low

IENL

ADDRESS : E3H

ADE WDTE BITE

RESET VALUE : 000-----

Enables or disables the interrupt individually

If flag is cleared, the interrupt is disabled.

0 : Disable

1 : Enable

Interrupt Request Register High

IRQH

INT0IF INT1IF T0IF

T1IF

ADDRESS : E4H

RESET VALUE : 0000----

Interrupt Request Register Low

IRQL

ADDRESS : E5H

ADIF WDTIF BITIF

RESET VALUE : 000-----

Shows the interrupt occurrence

0 : Not occurred

1 : Interrupt request is occurred

Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers

When an interrupt is occurred, the I-flag is cleared and dis-

able any further interrupt, the return address and PSW are

pushed into the stack and the PC is vectored to. Once in the

interrupt service routine the source(s) of the interrupt can

be determined by polling the interrupt request flag bits.

The interrupt request flag bit(s) must be cleared by soft-

ware before re-enabling interrupts to avoid recursive inter-

rupts. The Interrupt Request flags are able to be read and

written.

Apr. 2001 ver1.0

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