HMS87C13042A Datasheet, PDF (70/88 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C130XA/120XA/110XA
The time between when the Basic interval timer senses a
high on the RESET pin, and when the RESET pin (and
V_DD) actually reach their full value, is too long. In this sit-
uation, when the Basic interval timer times out, V_DD has
not reached the V_DD (min) value and the chip is, therefore,
not guaranteed to function correctly. For such situations,
we recommend that external R circuits be used to achieve
longer POR delay times ( Figure 18-5). The POR circuit
does not produce an internal reset when VDD declines
Note: When the device starts normal operation (exits the
reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be meet to
ensure operation. If these conditions are not met,
the device must be held in reset until the operating
conditions are met..
V_DD
RESET
INTERNAL POR
INTERNAL RESET
Basic Interval Timer Start
Figure 18-3 Time-out Sequence On Power-up (RESET Tied To V_DD): Fast V_DD Rise Time
V_DD
RESET
INTERNAL POR
INTERNAL RESET
Basic Interval Timer Start
Figure 18-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIED TO V_DD): SLOW V_DD RISE TIME
V_DD V_DD
D
R
R1
C
RESET
- External Power-On Reset circuit is required only if VDD
power-up is too slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
- R < 40 kΩ is recommended to make sure that voltage
drop across R does not violate the device electrical specifi-
cation.
- R1 = 100Ω to 1kΩ will limit any current flowing into
RESET from external capacitor C in the event of RESET
pin breakdown due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
Figure 18-5 EXTERNAL POWERON RESET CIRCUIT (FOR SLOW V_DD POWER-UP)
Apr. 2001 ver1.0
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