HY5V22GF Datasheet, PDF (7/11 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System clock
cycle time
CAS Latency = 3
CAS Latency = 2
Clock high pulse width
Clock low pulse width
Access time from clock
CAS Latency = 3
CAS Latency = 2
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
CLK to data output in
high Z-time
CAS Latency = 3
CAS Latency = 2
Symbol
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
-H
Min
Max
7.5
1000
10
2.5
-
2.5
-
5.4
6
2.7
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
5.4
-P
Min
Max
10
1000
10
3
-
3
-
6
-
6
3
-
2
-
1
-
2
-
1
-
2
-
1
-
2
-
1
-
1
-
6
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
HY5V22GF
Unit
Note
ns
ns
ns
1
ns
1
ns
2
ns
ns
3
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
1
ns
ns
ns
Rev. 0.3/Nov. 01
8