HY5V22GF Datasheet, PDF (1/11 Pages) Hynix Semiconductor – 4 Banks x 1M x 32Bit Synchronous DRAM

HY5V22GF
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY5V22G is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY5V22G is organized as 4banks of 1,048,576x32.
HY5V22G is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• JEDEC standard 3.3V power supply
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms
• 90Ball FBGA with 0.8mm of pin pitch
• Programmable Burst Length and Burst Type
• All inputs and outputs referenced to positive edge of
- 1, 2, 4, 8 or full page for Sequential Burst
system clock
- 1, 2, 4 or 8 for Interleave Burst
• Data mask function by DQM0,1,2 and 3
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
• Burst Read Single Write operation
ORDERING INFORMATION
Part No.
HY5V22GF-H
HY5V22GF-P
Clock Frequency
133MHz
100MHz
Power
Normal
Organization
4Banks x 1Mbits
x32
Interface
LVTTL
Package
90Ball FBGA
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3/Nov. 01