HY5DU573222AFM Datasheet, PDF (7/30 Pages) Hynix Semiconductor – 256M(8Mx32) GDDR SDRAM

HY5DU573222AFM
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
Extended Mode Register Set
H
Mode Register Set
H
Device Deselect
H
No Operation
Bank Active
H
Read
H
Read with Autoprecharge
Write
H
Write with Autoprecharge
Precharge All Banks
H
Precharge selected Bank
Read Burst Stop
H
Auto Refresh
H
Entry
H
Self Refresh
Exit
L
Entry
H
Precharge Power
Down Mode
Exit
L
Active Power
Entry
H
Down Mode
Exit
L
CKEn
X
X
X
X
X
X
X
X
H
L
H
L
H
L
H
CS0/
CS1
L
L
H
L
L
L
L
L
L
L
L
H
L
H
L
H
L
H
L
RAS
L
L
X
H
L
CAS
L
L
X
H
H
H
L
H
L
L
H
H
H
L
L
L
L
X
X
H
H
X
X
H
H
X
X
H
H
X
X
V
V
X
WE
ADDR
A8/
AP
BA Note
L
OP code
1,2,6
L
OP code
1,2,6
X
X
1
H
H
RA
V
1
L
H
CA
H
1,7
V
1,3,7
L
L
CA
H
1,7
V
1,4,7
H
X
1,5
L
X
L
V
1
L
X
1
H
X
1
H
1,6
X
X
1,6
H
X
1,6
H
1,6
X
X
1,6
H
1,6
X
1,6
V
X
1,6
1,6
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
6. Both of CS0 & CS1 should be enabled simultaneously.
Rev. 0.5 / Aug. 2003
7