HY5DU573222AFM Datasheet, PDF (22/30 Pages) Hynix Semiconductor – 256M(8Mx32) GDDR SDRAM

HY5DU573222AFM
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Sym
bol
Test Condition
25
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min);
DQ,DM and DQS inputs changing
twice per clock cycle; address and
control inputs changing once per
clock cycle
one chip active, the other chip
precarge standby
Operating Current
IDD1
Burst length=4, One bank active
tRC ≥ tRC(min), IOL=0mA
one chip active, the other chip
precarge standby
Precharge Standby
Current in Power Down
IDD2P ^{CKE ≤ VIL(max), tCK=min}
Mode
both chips precharge standby
Precharge Standby
Current in Non Power
Down Mode
CKE≥ VIH(min), /CS ≥ VIH(min),
IDD2N
tCK = min, Input signals are
changed one time during 2clks
both chips precharge standby
Active Standby Cur-
rent in Power Down
Mode
CKE ≤ VIL(max), tCK=min
IDD3P one chip active standby, the other
chip precharge standby
Active Standby Cur-
rent in Non Power
Down Mode
CKE ≥ VIH(min), /CS ≥
VIH(min), tCK=min, Input signals
IDD3N are changed one time during 2clks
one chip active standby, the other
chip precharge standby
Burst Mode Operating
Current
tCK ≥tCK(min),IoL=0mA
IDD4 All banks
both chips active
Auto Refresh Current
tRC ≥ tRFC(min),
IDD5 All banks active
both chips refresh
Self Refresh Current
IDD6 ^{CKE ≤ 0.2V}
both chips refresh
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4,
both chips and 4 bank interleaving
260
280
70
170
100
270
820
700
6
1100
Speed
28
33
36
240
220
210
260
240
230
60
50
50
150
120
120
90
70
70
250
200
200
740
620
570
700
600
600
6
6
6
950
820
720
Unit Note
4
200 mA 1
220 mA 1
50 mA
120 mA
70 mA
200 mA
570 mA 1
600 mA 1,2
6
mA
720 mA
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 0.5 / Aug. 2003
22