HY5DU573222AFM Datasheet, PDF (24/30 Pages) Hynix Semiconductor – 256M(8Mx32) GDDR SDRAM

HY5DU573222AFM
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Row Address to Column Address Delay for Read
Row Address to Column Address Delay for Write
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Last Data-In to Read Command
Auto Precharge Write Recovery + Precharge Time
System Clock Cycle Time
CL=5
CL=4
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRRD
tCCD
tRP
tWR
tDRL
tDAL
tCK
tCH
tCL
tAC
tDQSCK
tDQSQ
Data-Out hold time from DQS
tQH
Clock Half Period
Data Hold Skew Factor
Input Setup Time
Input Hold Time
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-In Hold Time to DQS-In (DQ & DM)
tHP
tQHS
tIS
tIH
tDQSH
tDQSL
tDQSS
tDS
tDH
25
Min
Max
18
-
21
-
12
100K
6
-
3
-
4
-
1
-
6
-
3
-
2
-
9
-
2.5
6
-
-
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-
0.35
tHPmin
-tQHS
-
tCH/L
min
-
-
0.35
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85
1.15
0.35
-
0.35
-
28
Min
Max
16
-
17
-
10
100K
5
-
2
-
4
-
1
-
5
-
3
-
2
-
8
-
-
-
2.8
6
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-
0.35
tHPmin
-tQHS
-
tCH/L
min
-
-
0.35
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85
1.15
0.35
-
0.35
-
Unit Note
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
CK
CK
ns
ns
ns
ns 1,6
ns 1,5
ns 6
ns 2
ns 2
CK
CK
CK
ns 3
ns 3
Rev. 0.5 / Aug. 2003
24