HY57V643220CT Datasheet, PDF (7/12 Pages) Hynix Semiconductor – 4 Banks x 512K x 32Bit Synchronous DRAM

HY57V643220C
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
-47
-5
-55
-6
-7
-8
-P
-S
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
System clock
cycle time
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
4.7
5
5.5
6
7
8
10
10
ns
1000
1000
1000
1000
1000
1000
1000
1000
10
10
10
10
10
-10
10
12
ns
Clock high pulse width
tCHW 1.65 -
2
- 2.25 - 2.5 -
3
-
3
-
3
-
3
- ns 1
Clock low pulse width
tCLW
1.65 -
2
- 2.25 - 2.5 -
3
-
3
-
3
-
3
- ns 1
Access time from
clock
CAS Latency = 3
CAS Latency = 2
tAC3
tAC2
- 4.5 - 4.5 -
5
- 5.5 - 5.5 -
6
-
6
-
6 ns
2
-
6
-
6
-
6
-
6
-
6
-
6
-
6
-
6 ns
Data-out hold time
tOH
1.5 - 1.5 -
2
-
2
-
2
-
2
-
2
-
2
- ns 3
Data-Input setup time
tDS
1.3 - 1.5 - 1.5 - 1.5 - 1.75 -
2
-
2
-
2
- ns 1
Data-Input hold time
tDH
0.8 -
1
-
1
-
1
-
1
-
1
-
1
-
1
- ns 1
Address setup time
tAS
1.3 - 1.5 - 1.5 - 1.5 - 1.75 -
2
-
2
-
2
- ns 1
Address hold time
tAH
0.8 -
1
-
1
-
1
-
1
-
1
-
1
-
1
- ns 1
CKE setup time
tCKS
1.3 - 1.5 - 1.5 - 1.5 - 1.75 -
2
-
2
-
2
- ns 1
CKE hold time
tCKH
0.8 -
1
-
1
-
1
-
1
-
1
-
1
-
1
- ns 1
Command setup time
tCS
1.3 - 1.5 - 1.5 - 1.5 - 1.75 -
2
-
2
-
2
- ns 1
Command hold time
tCH
0.8 -
1
-
1
-
1
-
1
-
1
-
1
-
1
- ns 1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- ns
CLK to data output ^{CAS Latency = 3}
in high Z-time
CAS Latency = 2
tOHZ3
tOHZ2
-
4
- 4.5 -
5
- 5.5 - 5.5 -
6
-
6
-
6 ns
-
6
-
6
-
6
-
6
-
6
-
6
-
6
-
6 ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.8/Aug. 02
7