HY62LF16206B-DT12C Datasheet, PDF (6/11 Pages) Hynix Semiconductor – 128Kx16bit full CMOS SRAM

TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
ADDR
/CS1
tRC
tAA
tACS
CS2
tBA
/UB ,/ LB
/OE
Data
Out
High-Z
READ CYCLE 2(Note 2,3,4)
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
ADDR
Data
Out
tRC
tAA
tOH
Previous Data
HY62LF16206B-DT12C
tOH
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
tOH
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS1
/UB, /LB
CS2
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1, a high CS2 and low /UB
and/or /LB.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
Rev.00 /Apr. 2003
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