HY62KF08802B Datasheet, PDF (6/10 Pages) Hynix Semiconductor – 1M x 8bit 2.7 ~ 3.6V Super low Power FCMOS Slow SRAM

TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
ADDR
/CS1
tRC
tAA
tACS
CS2
/OE
Data
Out
High-Z
tOE
tCLZ(3)
tOLZ(3)
HY62KF08802B Series
tOH
tCHZ(3)
tOHZ(3)
Data Valid
READ CYCLE 2 (Note 1,2,4)
ADDR
Data
Out
tRC
tAA
tOH
Previous Data
READ CYCLE 3 (Note 1,2,4)
/CS1
tOH
Data Valid
CS2
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /CS1 and CS2 are in active status.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
Rev.00 / Jan.02
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