HY62KF08401C Datasheet, PDF (6/10 Pages) Hynix Semiconductor – 512Kx8bit full CMOS SRAM

HY62KF08401C Series
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
ADDR
/CS
tRC
tAA
tACS
tOH
tCHZ(3)
/OE
Data
Out
High-Z
tOE
tCLZ(3)
tOLZ(3)
READ CYCLE 2 (Note 1,2,4)
tRC
ADDR
Data
Out
tAA
tOH
Previous Data
tOHZ(3)
Data Valid
tOH
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
Data
Out
tACS
tCLZ(3)
Data Valid
tCHZ(3)
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS.
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
Rev.01 / Jun.01
5