HY5W6B6DLF-HE Datasheet, PDF (5/27 Pages) Hynix Semiconductor – 4Banks x1M x 16bits Synchronous DRAM

Preliminary
HY5W6B6DLF(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Low Power Synchronous DRAM
PASR
Extended
Mode
Register
Self refresh
logic & timer
Internal Row
Counter
CLK
1Mx16 Bank 3
Row
CKE
Row Active
Pre
1Mx16 Bank 2
1Mx16 Bank 1
CS
Decoder
1Mx16 Bank 0
RAS
CAS
WE
U/LDQM
Refresh
Column Active
Column
Pre
Decoder
Memory
Cell
Array
Column decoders
DQ0
DQ15
Bank Select
Column Add
Counter
A0
Address
A1
Register
Burst
Counter
A11
Mode Register
CAS Latency
Data Out Control
BA1
BA0
Rev. 0.1 / Feb. 2004
5