HY5W6B6DLF-HE Datasheet, PDF (25/27 Pages) Hynix Semiconductor – 4Banks x1M x 16bits Synchronous DRAM

Preliminary
HY5W6B6DLF(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
Special Operation for Low Power Consumption
Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole
memory array of the devices.
Data will not be retained once the device enters Deep Power Down Mode.
Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Current State
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
Idle
Deep Power Down Entry
H
L
L
H
H
L
Deep Power Down Deep Power Down Exit
L
H
X
X
X
X
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of
the clock, while CKE is low. The following diagram illustrates deep power down mode entry.
CLK
CKE
CS
RAS
CAS
WE
tRP
Precharge
if needed
Deep Power Down Entry
Rev. 0.1 / Feb. 2004
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