HY5W6B6DLF-HE Datasheet, PDF (15/27 Pages) Hynix Semiconductor – 4Banks x1M x 16bits Synchronous DRAM

Preliminary
HY5W6B6DLF(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
CURRENT STATE TRUTH TABLE (Sheet 4 of 4)
Current
State
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
Write
Recovering
H
X
X
X
X
X
LL L L
OP CODE
LL L H X
X
L L H L BA
X
Write
L L H H BA
Row Add.
Recovering
with Auto ^{L H L L BA Col Add. A10}
Precharge _{L H L H BA Col Add. A10}
LHH H X
X
HX X X
LL L L
LL L H
LLH L
LLHH
Refreshing ^{L H L L}
LH L H
LHH H
X
X
OP CODE
X
X
BA
X
BA
Row Add.
BA Col Add. A10
BA Col Add. A10
X
X
HX X X
LL L L
LL L H
LLH L
Mode
Register
LLHH
LH L L
Accessing _{L H L H}
LHH H
X
X
OP CODE
X
X
BA
X
BA
Row Add.
BA Col Add. A10
BA Col Add. A10
X
X
HX X X
X
X
Description
Action
Notes
Device Deselect
No Operation:
Row Active after tDPL
Mode Register Set ILLEGAL
13,14
Auto or Self Refresh ILLEGAL
13
Precharge
ILLEGAL
4,13
Bank Activate
ILLEGAL
4,12
Write/WriteAP
ILLEGAL
4,12
Read/ReadAP
ILLEGAL
4,9,12
No Operation
No Operation:
Precharge after tDPL
Device Deselect
No Operation:
Precharge after tDPL
Mode Register Set ILLEGAL
13,14
Auto or Self Refresh ILLEGAL
13
Precharge
ILLEGAL
13
Bank Activate
ILLEGAL
13
Write/WriteAP
ILLEGAL
13
Read/ReadAP
ILLEGAL
13
No Operation
No Operation:
idle after tRC
Device Deselect
No Operation:
idle after tRC
Mode Register Set ILLEGAL
13,14
Auto or Self Refresh ILLEGAL
13
Precharge
ILLEGAL
13
Bank Activate
ILLEGAL
13
Write/WriteAP
ILLEGAL
13
Read/ReadAP
ILLEGAL
13
No Operation
No Operation:
idle after 2 clock cycles
Device Deselect
No Operation:
idle after 2 clock cycles
Rev. 0.1 / Feb. 2004
15