HY5PS56421LF-E3 Datasheet, PDF (4/35 Pages) Hynix Semiconductor – 256Mb DDR2 SDRAM

1. Description
HY5PS56421(L)F
HY5PS56821(L)F
HY5PS561621(L)F
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD=1.8V
• VDDQ=1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe suupported (x8 only)
• Self-Refresh High Temperature Entry
Ordering Information
Operating Frequency
Part No.
Grade tCK(ns) CL
Configuration Package
tRCD tRP
HY5PS56421(L)F-X*
-E3
64Mx4
60Ball
5
3
3
3
FBGA
-E4
5
4
4
4
HY5PS56821(L)F-X*
32Mx8
-C4
3.75
4
4
4
HY5PS561621(L)F-X*
16Mx16
84Ball
FBGA
-C5
3.75
5
5
5
Note: -X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
-Y5
3
5
5
5
Unit
Clk
Clk
Clk
Clk
Clk
-Y6
3
6
6
6
Clk
Rev 1.0/July. 2004
4