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| HY5PS56421LF-E3 Datasheet, PDF (27/35 Pages) Hynix Semiconductor – 256Mb DDR2 SDRAM | |||
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HY5PS56421(L)F
HY5PS56821(L)F
HY5PS561621(L)F
Fig. a Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
VDDQ
tIS,
tIH,
tDS
tDH
tIS,
tIH,
tDS
tDH
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
Vss
nominal
slew rate
nominal
slew rate
VREF to ac
region
Delta TF
Delta TR
Setup Slew Rate
Falling Signal
=
VREF(dc)-VIL(ac)max
Delta TF
Setup Slew Rate
Rising Signal
=
VIH(ac)min-VREF(dc)
Delta TR
Rev 1.0 / July. 2004
27
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