STAC9704 Datasheet, PDF (35/49 Pages) Hynix Semiconductor – Multimedia Audio Codec for AC97

SigmaTel, Inc.
Table 20: Warm Reset
STAC9704/7
PARAMETER
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
SYMBOL
Tsync_high
Tsync_2clk
MIN
-
162.8
TYP
1.3
-
MAX
-
-
UNITS
us
ns
7.3 Clocks
Figure 16: Clocks
Tclk_low
BIT_CLK
SYNC
Tclk_high
Tclk_period
Tsync_high
Tsync_low
Tsync_period
Table 21: Clocks
PARAMETER
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BLT_CLK high pulsewidth (note 1)
BIT_CLK low pulse width (note 1)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low_pulse width
SYMBOL
Tclk_period
Tclk_high
Tclk_low
Tsync_period
Tsync_high
Tsync_low
MIN
-
-
-
32.56
32.56
-
-
-
-
TYP
12.288
81.4
-
40.7
40.7
48.0
20.8
1.3
19.5
MAX
-
-
750
48.84
48.84
-
-
-
-
UNITS
MHz
ns
ps
ns
ns
kHz
us
us
us
Notes: 1) Worst case duty cycle restricted to 40/60.
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10/02/98